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September 2006 rev 0.5
PCS2I2310ANZ
3.3V SDRAM Buffer for Mobile PCS with 4 SO-DIMMs
Features
* * * * * * * * * * One input to 10 output buffer/driver Supports up to four SDRAM SO-DIMMs Two additional outputs for feedback Serial interface for output control Low skew outputs Up to 133MHz operation Multiple VDD and VSS pins for noise reduction Dedicated OE pin for testing Space-saving 28 Pin SSOP package 3.3V operation
Functional Description
The PCS2I2310ANZ is a 3.3V buffer designed to distribute high-speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133MHz, thus making it compatible with Pentium II(R)i processors. The PCS2I2310ANZ also includes a serial interface (IIC), which can enable or disable each output clock. The IIC is Slave Receiver only and is Standard mode compliant. IIC Master can write into the IIC registers but cannot read back. The first two bytes after address should be ignored by IIC Block and data is valid after these two bytes as given in IIC Byte Flow Table. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE.
i
Pentium II is a registered trademark of Intel Corporation
Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDATA Serial Interface Decoding SCLOCK SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 OE
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.5
Pin Configuration 28 Pin SSOP Package-- Top View
PCS2I2310ANZ
VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM8 VSS VDDIIC SDATA
1 2 3 4 5 6 7 8 9 10 11 12 16pi TSSOP 13 14
28 27 26 25 24 23
VDD SDRAM7 SDRAM6 VSS VDD SDRAM5 SDRAM4 VSS OE VDD SDRAM9 VSS VSSIIC SCLOCK
PCS2P2310ANZ
22 21 20 19 18 17 16 15
28 pin SSOP
Pin Description Pins
1, 5, 10, 19, 24, 28 4, 8, 12, 17, 21, 25 13 16 9 20 14 15 2, 3, 6, 7 22, 23, 26, 27 11, 18 VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-3] SDRAM [4-7] SDRAM [8-9]
Name
Type
P P P P I I I/O I O O O Ground
Description
3.3V Digital voltage supply 3.3V Serial interface voltage supply Ground for serial interface Input clock, 5V tolerant Output Enable, three-states outputs when LOW. Internal pull-up to VDD Bi-directional Serial data pin. Internal pull-up to VDD. 5V tolerant Serial clock input. Internal pull-up to VDD. 5V tolerant SDRAM byte 0 Clock Outputs SDRAM byte 1 Clock Outputs SDRAM byte 2 Clock Outputs
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Device Functionality OE
0 1
PCS2I2310ANZ
Byte 1: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SDRAM [0-17]
High-Z 1 x BUF_IN
Pin #
27 26 23 22 -----
Description
SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Unused Unused Unused Unused
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits can be programmed to either "0" or "1". * Serial interface address for the PCS2I2310ANZ is:
Byte 2: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable R/W
----
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
18 11 -------
Description
SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved
Byte 0: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
----7 6 3 2 Unused Unused Unused Unused
Description
SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up.
IIC Byte Flow Byte
1 2 3 4 5 6
Description
IIC Address Command (dummy value, ignored) Byte Count (dummy value, ignored) IIC Data Byte 0 IIC Data Byte 1 IIC Data Byte 2
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Absolute Maximum Ratings Symbol
VDD VIN VINB TSTG TJ TDV
PCS2I2310ANZ
Parameter
Supply Voltage to Ground Potential DC Input Voltage (Except BUF_IN) DC Input Voltage (BUF_IN) Storage Temperature Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
Rating
-0.5V to +7.0 -0.5V to VDD + 0.5 -0.5V to +7.0 -65C to +150 150 2000
Unit
V V V C C V
Operating Conditions Parameter
VDD TA CL CIN tPU
Description
Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic)
Min
3.135 0 20 0.05
Max
3.465 70 30 7 50
Unit
V C pF pF ms
Electrical Characteristics Parameter
VIL VILIIC VIH VOL VOH ICC IOZ IOFF ICC Ii IDD IDD IDD IDD IDD IDD IDDS
Description
Input LOW Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage1 Output HIGH Voltage1 Quiescent Supply Current High Impedance Output Current OffState Current (for SCL ,SDATA) Change in Supply Current Input Leakage Supply Current Supply Current1 Supply Current1 Supply Current1 Supply Current1 Supply Current1 Supply Current
1
Test Conditions
Except serial interface pins For serial interface pins only
Min
2.0
Typ
Max
0.8 0.7 0.4
Unit
V V V V V A A A A A mA mA mA mA mA mA A
IOL= 25 mA IOH = -36 mA VDD= 3.465V, Vi = VDD or GND IO =0 VDD= 3.465V, Vi = VDD or GND VDD= 0V, Vi = 0V or 5.5V VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND VDD= 3.465V or GND (Applicable to all Input Pins) Unloaded outputs, 133MHz Loaded outputs, 30pF, 133MHz Unloaded outputs, 100MHz Loaded outputs, 30pF,100MHz Unloaded outputs, 66.67MHz Loaded outputs, 30pF ,66.67MHz BUF_IN=VDD or VSS, all other inputs at VDD
2.4 50 100 10 50 500 -5 +5 266 360 200 290 150 185 500
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Switching Characteristics1 Parameter
fmax tD t3 t4 t5 t6 t7 tPLZ, tPHZ tPZL, tPZH tr tf Duty Cycle
PCS2I2310ANZ
Name
Maximum Operating Frequency
2,3
Test Conditions
Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V
3 3 3
Min
45.0 1 1 1 1 1 1 6
Typ
50.0 2 2 150 2.7 2.7 3 3
Max
133 55.0 4 4 225 3.5 3.5 5 5 250
Unit
MHz % V/nS V/nS pS nS nS nS nS nS nS
= t2 / t1
3 3
Rising Edge Rate
Falling Edge Rate
Output to Output Skew
All outputs equally loaded Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS CL = 10pF CL = 400pF CL = 10pF CL = 400pF 20
SDRAM Buffer LH Prop. Delay SDRAM Buffer Enable Delay Rise Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 Fall Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3
3 3
SDRAM Buffer HL Prop. Delay SDRAM Buffer Disable Delay
250
Note: 1 .All parameters specified with loaded outputs. 2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS 3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S1 2 * VDD Open VSS
VDD 500 VI PULSE GENERATOR RT D.U.T 500 VO
CL
TEST t6/t7 tPLZ/tPZL tPHZ/tPZH
S1 Open 2* VDD VSS
Figure 1. Load circuit for Switching times
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
SDRAM Enable and Disable Times
VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load
PCS2I2310ANZ
VI OE INPUT GND
VM
VDD
tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VDD OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled Outputs disabled
tPZL
VM VX
tPZH
VY VM
Outputs enabled
Figure 2. 3-State Enable and Disable times
Test Circuit for IIC Rise and Fall Times
VO = 3.3V
RL = 1k
DUT CL = 10pF or CL = 400pF GND
Figure 3. Test Circuit for IIC
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Switching Waveforms Duty Cycle Timing
t1 t2
1.5 V 1.5 V 1.5 V
PCS2I2310ANZ
All Outputs Rise/Fall Time
2.4 V
OUTPUT
0.4 V
2.4 V 0.4 V
3.3 V 0V
t3
t4
Output - Output Skew
1.5 V
OUTPUT
1.5 V
OUTPUT
t5
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
t7
Test Circuits
+3.3V
TEST CIRCUIT VDD
+3.3V
0.1uF
CLKOUT OUTPUT VDD CLOAD
0.1uF
GND
GND
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
PCS2I2310ANZ
Rs CPUCLK BUF_IN Rs SDRAMX
SDATA SCLK VDD
SDATA Ct SCLK VDD
Cd = Decoupling Capacitor
VSS
Ct = Optional EMI-Reducing Capacitor Rs = Series Terminating Resistors X = 0 to 10
Cd = 0.1 F PCS2I2310ANZ SSOP 28
Summary
* * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1F. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * * * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF. A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. If a Ferrite Bead is used, a 10F-22F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
IIC Serial Interface Information
The information in this section assumes familiarity with IIC programming.
PCS2I2310ANZ
How to program PCS2I2310ANZ through IIC:
* * * * * * * * * * * * * * Master (host) sends a start bit. Master (host) sends the write address D3 (H). PCS2I2310ANZ device will acknowledge. Master (host) sends the Command Byte. PCS2I2310ANZ device will acknowledge the Command Byte. Master (host) sends a Byte count PCS2I2310ANZ device will acknowledge the Byte count. Master (host) sends the Byte 0 PCS2I2310ANZ device will acknowledge Byte 0 Master (host) sends the Byte 1 PCS2I2310ANZ device will acknowledge Byte 1 Master (host) sends the Byte 2 PCS2I2310ANZ device will acknowledge Byte 2 Master (host) sends a Stop bit.
Controller (Host)
Start Bit Slave Address D3(H)
PCS2I2310ANZ (slave/receiver)
ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Package Information 28L SSOP (209 mil)
PCS2I2310ANZ
Symbol
A A1 A2 D L E E1 R1 b b1 c c1 L1 e
Dimensions Inches Millimeters Min Max Min Max
.... 0.002 0.065 0.394 0.021 0.295 0.197 0.004 0.009 0.009 0.004 0.004 0.079 ... 0.073 0.409 0.037 0.319 0.220 .... 0.015 0.013 0.010 0.008 ... 0.05 1.65 10.00 0.55 7.50 5.00 0.09 0.22 0.22 0.09 0.09 2.0 ... 1.85 10.40 0.95 8.10 5.60 ..... 0.38 0.33 0.25 0.21
0.050REF 0.026 BSC 0 8
1.25 REF 0.65 BSC 0 8
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Ordering Information Part Number
PCS2P2310ANZG-28-AT PCS2P2310ANZG-28-AR PCS2I2310ANZG-28-AT PCS2I2310ANZG-28-AR
PCS2I2310ANZ
Marking
2P2310ANZG 2P2310ANZG 2I2310ANZG 2I2310ANZG
Package Type
28-pin SSOP -Tube, Green 28-pin SSOP -Tape and Reel, Green 28-pin SSOP -Tube, Green 28-pin SSOP -Tape and Reel, Green
Operating Range
Commercial Commercial Industrial Industrial
Device Ordering Information
PCS2I2310ANZG-28-AR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
PCS2I2310ANZ
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I2310ANZ Document Version: 0.5
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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